In order to fabricate an electronic circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), a number of processes must be performed. For example, the first step is to design the circuit at a “behavioral” level. The behavioral description is the top level of the design hierarchy. A hardware description characterizes the circuit using actual hardware components and is the lowest level of the design hierarchy.
The behavioral description is typically a block diagram or netlist that describes the various functions of the circuit in relatively general terms. The hardware description is based on the behavioral description. The behavioral description does not have enough specificity to fully enable a circuit manufacturer to implement the circuit design. The conventional approach is to manually generate an electronic file that characterizes the circuit at the hardware level in a programming language such as hardware description language (HDL). A design engineer goes through the behavioral description on a component-by-component basis and generates the necessary code sets in the programming language. This approach is labor intensive and subject to human error.
Once the electronic file has been manually generated, a complex verification process is required. In the case of the ASIC design, the functionality is extensively verified from a model of the circuit written in C-code. A select set of C-code input simulation vectors (i.e. input sequences) are then also applied to the HDL circuit model. In this co-simulation, the output vectors from the HDL model are compared bit by bit to the corresponding output vectors from the C-code model to establish a correspondence between the performance verified by the C-code model and the hardware actually being fabricated. This is typically required due to the complexity of the ASIC chip and the difficulty in performing a functional simulation in HDL, the complexity and cost of the ASIC fabrication process, and the need for a high level of certainty as to the functionality and first pass success of the electronic file and its subsequent fabrication. The manual generation of the C model also requires detailed knowledge of the C programming language, which increases the labor costs that are associated with fabrication. Once the electronic file has been verified, it is typically converted to the format used by the manufacturer using a conversion program such as Synopsis. After the electronic file has been converted, the manufacturer fabricates the circuit.
In U.S. Pat. No. 6,077,303 to Mandell et al. and co-pending application “Application Specific Integrated Circuit Design Tool and File Structure” Ser. No. 09/918,596, filed Jul. 31, 2001, and assigned to The Boeing Company, a design tool and method for simplifying the design of ASICs is disclosed. The design tool and method generates symbolic and numeric equations. In situations involving relatively less complex, small to medium ASICs, the symbolic equations that are generated by the design tool are finite and computationally feasible. In other words, the symbolic equations require a limited amount of computer storage and running time to be further simplified. However, when more complex circuits are involved (such as large ASICs and/or circuits including cascaded finite impulse response (FIR) filters, closed-loops, and other complex components), the resulting set of symbolic equations become large enough to overflow the memory that is available to the workstation and/or the capability of the symbolic manipulation tool that is used to compare the equations.